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INTEGRATED CIRCUITS
DATA SHEET
TZA3034 SDH/SONET STM1/OC3 postamplifier
Product specification Supersedes data of 1999 Nov 03 2002 Jul 19
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
FEATURES * Pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range and less external component count * Wideband operation from 1.0 kHz to 150 MHz typical * Applicable in 155 Mbits/s SDH/SONET receivers * Single supply voltage from 3.0 to 5.5 V * Positive Emitter Coupled Logic (PECL) compatible data outputs * Programmable input signal level detection which can be adjusted using a single external resistor * On-chip DC offset compensation without external capacitor. APPLICATIONS * Digital fibre optic receiver in short, medium and long haul optical telecommunications transmission systems or in high speed data networks * Wideband RF gain block. ORDERING INFORMATION TYPE NUMBER TZA3034T TZA3034TT TZA3034U PACKAGE NAME SO16 TSSOP16 - DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm bare die in waffle pack carriers; die dimensions 1.55 x 1.55 mm GENERAL DESCRIPTION
TZA3034
The TZA3034 is a high gain limiting amplifier that is designed to process signals from fibre optic preamplifiers like the TZA3033. It is pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range, and needs less external components. Capable of operating at 155 Mbits/s, the chip has input signal level detection with a user-programmable threshold. The data and level detection status outputs are differential outputs for optimum noise margin and ease of use.
VERSION SOT109-1 SOT403-1 -
2002 Jul 19
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
BLOCK DIAGRAM
TZA3034
handbook, full pagewidth
TEST 2 (2, 10, 15, 21, 26) DC-OFFSET COMPENSATION DIN DINQ 4 (7) 5 (8) A1 A2 A3
TZA3034
(24) 13 (23) 12 (16) 8 (18) 10
DOUT DOUTQ JAM ST STQ
25 k RECTIFIER RSET Vref 16 (30) 15 (29) 1 k A4 BAND GAP REFERENCE
(17) 9
(3, 4, 6, 9) 3 AGND
(1, 14) 1
(11, 12) 6 VCCA
(13) 7 CF
(19, 20, 22, 25) 11
(27, 28) 14
MGR281
SUB
DGND
VCCD
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
handbook, halfpage
SUB 1 TEST 2 AGND 3 DIN 4
16 RSET 15 Vref 14 VCCD 13 DOUT
handbook, halfpage
SUB 1 TEST 2 AGND 3 DIN 4
16 RSET 15 Vref 14 VCCD 13 DOUT
TZA3034T
DINQ 5 VCCA 6 CF 7 JAM 8
MGR282
TZA3034TT
12 DOUTQ 11 DGND 10 ST 9 STQ DINQ 5 VCCA 6 CF 7 JAM 8
MBK997
12 DOUTQ 11 DGND 10 ST 9 STQ
Fig.2 Pin configuration of TZA3034T.
Fig.3 Pin configuration of TZA3034TT.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
PINNING SYMBOL SUB TEST AGND DIN DINQ VCCA CF PIN PAD TZA3034T TYPE(1) TZA3034U TZA3034TT 1 2 3 4 5 6 7 1, 14 2, 10, 15, 21, 26 3, 4, 6, 9 7 8 11, 12 13 S - S I I S A DESCRIPTION
TZA3034
substrate pin; must be at the same potential as pin AGND for test purpose only; to be left open in the application analog ground; must be at the same potential as pin DGND differential input; complementary to pin DINQ; DC bias level is set internally at approximately 2.1 V differential input; complementary to pin DIN; DC bias level is set internally at approximately 2.1 V analog supply voltage; must be at the same potential as pin VCCD input for connection of capacitor to set time constant of level detector input filter (optional); the capacitor should be connected between VCCA and pin CF PECL-compatible input; controls the output buffers, pins DOUT and DOUTQ; when a LOW signal is applied, the output buffers will follow the input signal; when a HIGH signal is applied, the output buffers will latch into LOW and HIGH states respectively; when not connected, pin JAM is actively pulled LOW PECL-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is HIGH; complementary to pin ST PECL-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is LOW; complementary to pin STQ digital ground; must be at the same potential as pin AGND PECL-compatible differential output; this pin will be forced into a HIGH condition when pin JAM is HIGH; complementary to pin DOUT PECL-compatible differential output; this pin will be forced into a LOW condition when pin JAM is HIGH; complementary to pin DOUTQ digital supply voltage; must be at the same potential as VCCA band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 k input signal level detector threshold setting; nominal DC voltage is VCCA - 1.5 V; threshold level is set by connecting an external resistor between VCCA and pin RSET or by forcing a current into pin RSET; default value for this resistor is 180 k which corresponds with approximately 4 mV (p-p) differential input signal not connected
JAM
8
16
I
STQ
9
17
O
ST
10
18
O
DGND DOUTQ DOUT
11 12 13
19, 20, 22, 25 23 24
S O O
VCCD Vref RSET
14 15 16
27, 28 29 30
S O A
n.c. Note
-
5, 31, 32
-
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
2002 Jul 19
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
FUNCTIONAL DESCRIPTION The TZA3034 accepts up to 155 Mbits/s SDH/SONET data streams, with amplitudes from 2 mV up to 1.5 V (p-p) single-ended. The input signal will be amplified and limited to differential PECL output levels (see Fig.1). The input buffer A1 presents an impedance of approximately 4.5 k to the data stream on the inputs pin DIN and pin DINQ. The input can be used both single-ended and differential, but differential operation is preferred for better performance. Because of the high gain of the postamplifier, a very small offset voltage would shift the decision level in such a way that the input sensitivity decreases drastically. Therefore a DC offset compensation circuit is implemented in the TZA3034, which keeps the input of buffer A3 at its toggle point in the absence of any input signal. An input signal level detection is implemented to check if the input signal is above the user-programmed level. The outcome of this test is available at the PECL outputs, pins ST and STQ. This flag can also be used to prevent the PECL outputs pins DOUT and DOUTQ from reacting to noise in the absence of a valid input signal, by connecting pin STQ to pin JAM. This guarantees that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. PECL logic The logic level symbol definitions for PECL are shown in Fig.4. Input biasing The inputs, pins DIN and DINQ, are DC biased at approximately 2.1 V by an internal reference generator (see Fig.5). The TZA3034 can be DC coupled, but AC coupling is preferred. In case of DC coupling, the driving source must operate within the allowable input signal range (1.3 V to VCCA). Also a DC offset voltage of more than a few millivolts should be avoided, since the internal DC offset compensation circuit has a limited correction range.
TZA3034
If AC coupling is used to remove any DC compatibility requirement, the coupling capacitors must be large enough to pass the lowest input frequency of interest. For example, 1 nF coupling capacitors react with the internal 4.5 k input bias resistors to yield a lower -3 dB frequency of 35 kHz. This then sets a limit on the maximum number of consecutive pulses that can be sensed accurately at the system data rate. Capacitor tolerance and resistor variation must be included for an accurate calculation. DC-offset compensation A control loop connected between the inputs of buffer A3 and amplifier A1 (see Fig.1) will keep the input of buffer A3 at its toggle point in the absence of any input signal. Because of the active offset compensation which is integrated in the TZA3034, no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain, which is set at approximately 850 Hz. Input signal level detection The TZA3034 allows for user-programmable input signal level detection and can automatically disable the switching of the PECL outputs if the input signal is below a set threshold. This prevents the outputs from reacting to noise in the absence of a valid input signal, and insures that data will only be transmitted when the signal-to-noise ratio of the input signal is sufficient for low bit-error-rate system operation. Complementary PECL flags (pins ST and STQ) indicate whether the input signal is above or below the programmed threshold level. The input signal is amplified and rectified before being compared to a programmable threshold reference. A filter is included to prevent noise spikes from triggering the level detector. This filter has a nominal 1 s time constant and additional filtering can be achieved by using an external capacitor between VCCA and pin CF (the internal driving impedance nominally is 25 k). The resultant signal is then compared to a threshold current through pin RSET. This current can be set by connecting an external resistor between VCCA and pin RSET, or by forcing a current into pin RSET (see Fig.6).
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
The relationship between the threshold current and the detected input voltage is approximately: I RSET = 0.0018 x ( V DIN - V DINQ ) [ A ] In the formulas (1) and (3), the voltage on pin DIN and pin DINQ is measured as peak-to-peak value. Since the voltage on pin RSET is held constant at 1.5 V below VCCA, the current flowing into this pin will be: 1.5 I RSET = ------------ [ A ] R ADJ (2) (1) Dissipation
TZA3034
Since the thermal resistance from junction to ambient Rth(j-a) of the TSSOP package is higher than the thermal resistance of the SO package (see Chapter "Thermal characteristics"), the dissipation should be considered when using the TZA3034TT version. The formula to calculate the worst case die temperature is: T j = T amb + R th ( j - a ) x P max where Tj = junction temperature Tamb = ambient temperature Rth(j-a) = thermal resistance from junction to ambient Pmax = maximum power dissipation. For the TZA3034T (SO package), the worst case die temperature Tj = 85 + 115 x 0.3 = 119.5 C which is below the maximum operating temperature. For the TZA3034TT (TSSOP package), the worst case die temperature Tj = 85 + 150 x 0.3 = 130 C which is higher than the maximum operating temperature, and therefore strongly discouraged. It is recommended to lower the thermal resistance from junction to ambient, e.g. by means of a dedicated board layout. However, if the ambient temperature is limited to 75 C or the power supply is limited to 3.3 0.3 V, the junction temperature will stay below the maximum value without further precautions. PECL output circuits The output circuit of ST and STQ is given in Fig.7. The output circuit of DOUT and DOUTQ is given in Fig.8. Some PECL termination schemes are given in Fig.9. (4)
Combining these two formulas results in a general formula to calculate RADJ for a given input signal level detection: 830 R ADJ = --------------------------------------- [ ] ( V DIN - V DINQ ) (3)
Example: Detection should occur if the differential voltage of the input signals drops below 4 mV (p-p). In this case, a reference current of 0.0018 x 0.004 = 7.2 A should flow into pin RSET. This can be set using a current source or simply by connecting a resistor of the appropriate value. The resistor must be connected between VCCA and pin RSET. In this example the value would be: 830 R ADJ = -------------- = 207.5 k 0.004 The hysteresis is fixed internally at 3 dB electrical. In the example of above, a differential level below 4 mV (p-p) of the input signal will drive pin ST to LOW, and an input signal level above 5.7 mV (p-p) will drive pin ST to HIGH. A function is provided to automatically disable the signal transmission when the chip senses that the input signal is below the programmed threshold level. This function can be put into operation by connecting pin JAM with pin STQ. When the input signal is below the programmed threshold level, the data outputs are then forced to a predetermined state (pin DOUT = LOW and pin DOUTQ = HIGH). Response time of the input signal level detection circuit is determined by the time constant of the input capacitors, together with the filter time constant (1 s internal plus the additional capacitor at pin CF). For SDH/SONET applications, couple capacitors of 1.5 nF are recommended, leading to a high-pass frequency of approximately 30 kHz and a maximum assert time of 30 s.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
handbook, halfpage
VCC VOH(max) VOH(min)
(1)
(2)
VOL(max) VOL(min)
MGS812
GND
(1) Output signal on pins DOUT or ST; complementary to output signal (2). (2) Output signal on pins DOUTQ or STQ; complementary to output signal (1)
Fig.4 Logic level symbol definitions for PECL outputs.
VCC handbook, halfpage
DIN 4.5 k
DINQ 4.5 k
2.1 V
1 mA
MGR958
Fig.5 Data input circuit DIN and DINQ.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
handbook, halfpage
VCCA
RADJ VRSET RSET IRSET
TZA3034
MGS813
VRSET = VCCA - 1.5 V.
Fig.6 level detect input circuit RSET.
handbook, halfpage
VCC VHIGH
VLOW
ST
10 k
MGS814
Output STQ is complementary to output ST.
Fig.7 PECL output circuit ST and STQ.
VCC handbook, halfpage 105 105
DOUT DOUTQ
0.5 mA 9 mA 0.5 mA
MGR247
Fig.8 PECL output circuit DOUT and DOUTQ.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
handbook, full pagewidth
VCC - 2 V R1 = 50 VI VIQ VO Zo = 50 VOQ
MGR248
R1 = 50
handbook, full pagewidth
VCC = 3.3 V R1 = 127 VI VIQ VO Zo = 50 VOQ R2 = 82.5 R2 = 82.5 R1 = 127
GND
MGR249
handbook, full pagewidth
VCC = 5.0 V R1 = 83.3 VI VIQ VO Zo = 50 VOQ R2 = 125 R2 = 125 R1 = 83.3
GND
MGR250
Fig.9 PECL output termination schemes.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134. SYMBOL VCC Vn supply voltage DC voltage pins DIN, DINQ, CF, JAM and RSET pins STQ, ST, DOUTQ and DOUT pin Vref In DC current pins DIN, DINQ, CF and JAM pins STQ, ST, DOUTQ and DOUT pin Vref pin RSET Ptot Tstg Tj Tamb HANDLING total power dissipation storage temperature junction temperature ambient temperature -1 -25 -2 -2 - -65 - -40 +1 +10 +2.5 +2 300 +150 150 +85 -0.5 VCC - 2 -0.5 PARAMETER MIN. -0.5
TZA3034
MAX. +6 VCC + 0.5 VCC + 0.5 +3.2 V V V V
UNIT
mA mA mA mA mW C C C
This device is ESD sensitive and should be handled with care. Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can be obtained by bonding the VCC and GND pads first, the remaining pads may then be bonded to their external connections in any order. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER SO16 package TSSOP16 package Note 1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single-sided 57 x 57 x 1.6 mm FR4 epoxy printed-circuit board with 35 m thick copper traces. The measurements are performed in still air. CONDITION VALUE 115 150 UNIT K/W K/W
thermal resistance from junction to ambient note 1
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
CHARACTERISTICS For typical values Tamb = 25 C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages are measured with respect to ground; unless otherwise specified. SYMBOL Supply VCC ICCD ICCA Ptot Tj Tamb Vi(se)(p-p) Vi(dif)(p-p) VI VIO(eq) VIO(cor) Ri Ci Vn(i)(rms) supply voltage digital supply current analog supply current total power dissipation junction temperature ambient temperature notes 1 and 2 note 2 notes 1 and 2 3 - - - -40 -40 note 3 note 3 0.002 0.004 1.3 - note 4; positive note 4; negative input resistance input capacitance equivalent input RMS noise voltage single-ended single-ended; note 5 notes 5 and 6 - - 2.9 - - 3.3 18 15 110 - +25 - - 2.1 - 3 -3 4.5 - 40 5.5 31 24 300 +125 +85 V mA mA mW C C V V V V mV mV k pF V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Input signal pins DIN and DINQ single-ended input signal voltage (peak-to-peak) differential input signal voltage (peak-to-peak) absolute input signal voltage equivalent input signal offset voltage input offset voltage correction 1.5 3.0 VCCA 50 - - 7.6 2.5 60
Input signal level detect pin RSET IRSET VRSET Vth(p-p) reference current reference voltage threshold adjusting range (single-ended and peak-to-peak) hysteresis filter resistance filter time constant CF = 0; note 5 notes 5 and 7 referred to VCCA 5 - - 60 VCCA - 1.4 12 A V mV VCCA - 1.65 VCCA - 1.5
Vi = 155 Mbit/s PRBS 2 27 - 1 sequence; note 5 electrically measured 2 14 0.5 VCC - 1.89 VCC - 1.1 - - - -
hys RF tF VOL VOH tr tf tPWD f-3dB(l)
3 25 1.0 - - 1.5 1.5 - 0.85
6 41 2.0 VCC - 1.6 VCC - 0.9 2.2 2.2 0.3 1.5
dB k s V V ns ns ns kHz
PECL output pins DOUT and DOUTQ LOW-level output voltage HIGH-level output voltage rise time fall time pulse width distortion low frequency -3 dB point note 8 note 8 20% to 80%; note 5 80% to 20%; note 5 note 5
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
SYMBOL f-3dB(h) VOL VOH CL
PARAMETER high frequency -3 dB point LOW-level output voltage HIGH-level output voltage load capacitance
CONDITIONS - note 8 note 8 RL = RL = 1 k RL = 50
MIN. 150 - - - - - - -
TYP. -
MAX.
UNIT MHz
PECL output pins ST and STQ VCC - 1.89 VCC - 1.1 - - - - note 9 -20 VCC - 1.6 VCC - 0.9 20 100 1000 VCC - 1.49 - +20 V V pF pF pF
PECL input pin JAM VIL VIH II(JAM) LOW-level input voltage HIGH-level input voltage JAM input current V V A VCC - 1.165 -
Reference voltage output pin Vref Vref Notes 1. PECL outputs (pins DOUT, DOUTQ, ST and STQ) are not connected. 2. Maximum currents are specified at Tj = 125 C, VCC = 5.5 V and worst case processing. 3. 2 mV (p-p) single-ended is the minimum input signal to achieve full clipping of the output signal. Typical an input signal of 0.5 mV (p-p) single-ended results in a Bit Error Rate (BER) of less than 10-10. 4. If the input is DC coupled, the preceding amplifier's output offset voltage should not exceed these limits, in order to avoid malfunctioning of the DC offset compensation circuit. 5. Specifications guaranteed by design and characterisation. Each device is tested at full operating speed to guarantee RF functionality. 6. total output RMS noise Input RMS noise = -------------------------------------------------------------low frequency gain reference voltage note 10 1.165 1.20 1.235 V
7. The reference current can be set by connecting a resistor between VCCA and pin RSET. The corresponding input signal level detect range is from 2 to 12 mV (p-p) single-ended. See Section "Input signal level detection" for detailed information. 8. RL = 50 connected to a level of VCC - 2 V (see Fig.9). 9. Internal pull-down resistor of 500 k to DGND. 10. Internal series resistor of 1 k.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TYPICAL PERFORMANCE CHARACTERISTICS
TZA3034
MGR944
handbook, halfpage
50
handbook, halfpage
1.5
MGR945
ICC (mA) 40
(1)
Vo(dif) (V)
1.4
(2)
1.3
30 1.2 20 1.1
10 -40
0
40
80
Tj (C)
120
1.0 -40
0
40
80
Tj (C)
120
PECL outputs not connected. (1) VCC = 5.5 V. (2) VCC = 3.0 V.
Vo(dif) = VDOUT - VDOUTQ.
Fig.10 Total power supply current as function of junction temperature.
Fig.11 Differential output voltage as function of junction temperature.
handbook, halfpage
1.4
MGR946
handbook, halfpage
2.0
MGR947
Vo(dif) (V) 1.3
t (ns) 1.8
1.6
1.2
1.4 tf tr
1.1
1.2
1 10-3
10-2
10-1
1 Vi(dif)(p-p) (V)
10
1.0 10-3
10-2
10-1
1 Vi(dif)(p-p) (V)
10
Vo(dif) = VDOUT - VDOUTQ.
Fig.12 Differential output voltage as function of differential input voltage.
Fig.13 Differential output rise time and fall time as function of differential input voltage.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
MGR948
MGR949
handbook, halfpage
2.0
handbook, halfpage
50
t (ns) 1.6
Vi(dif) (mV)
40
(1) (2)
1.2
30
(3)
0.8
20
(4)
0.4
10
0 -40
0 0 40 80 Tj (C) 120 0 10 20 30 40 IRSET (A) 50
Fig.14 Differential output rise time and fall time as function of junction temperature.
Vi(dif) = VDIN - VDINQ. (1) Input high threshold for 1 0 1 0 pattern (pin ST = HIGH). (2) Input high threshold for 27 - 1 PRBS pattern (pin ST = HIGH). (3) Input low threshold for 1 0 1 0 pattern (pin ST = LOW). (4) Input low threshold for 27 - 1 PRBS pattern (pin ST = LOW).
Fig.15 Status detect level as function of IRSET.
MGR950
MGR951
handbook, halfpage
40
handbook, halfpage
(1)
5
Vi(dif) (mV) 30
hys (dB) 4
(2)
3
20
(1) (2)
2
10
(3)
1
(4)
0 -40
0
40
80
Tj (C)
120
0 0 10 20 30 40 IRSET (A) 50
Vi(dif) = VDIN - VDINQ. (1) Input high threshold for IRSET = 45 A (pin ST = HIGH). (2) Input low threshold for IRSET = 45 A (pin ST = LOW). (3) Input high threshold for IRSET = 10 A (pin ST = HIGH). (4) Input low threshold for IRSET = 10 A (pin ST = LOW). (1) 1 0 1 0 pattern. (2) 27 - 1 PRBS pattern.
Fig.16 Status detect level as function of junction temperature.
Fig.17 Status detect hysteresis as function of IRSET.
2002 Jul 19
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
MGR952
MGR953
handbook, halfpage
4
handbook, halfpage
0.003
hys (dB) 3
(1) (2)
Ratio (A/V) 0.002
(1) (2)
2 0.001 1
0 -40
0 0 40 80 Tj (C) 120 0 10 20 30 40 IRSET (A) 50
(1) IRSET = 10 A. (2) IRSET = 45 A.
I RSET Ratio = ------------- where Vi(dif) = input low threshold (pin ST = LOW). V i ( dif ) (1) 27 - 1 PRBS pattern. (2) 1 0 1 0 pattern.
Fig.18 Status detect hysteresis as function of junction temperature.
Fig.19 Status detect ratio as function of IRSET.
MGR954
MGR955
handbook, halfpage
0.3
handbook, halfpage
1.55
t PWD (ns) 0.2
VRSET (V) 1.53
(1) (2)
0.1
1.51
0 10-3
10-2
10-1
1 Vi(dif)(p-p) (V)
10
1.49 -40
0
40
80
Tj (C)
120
Fig.20 Pulse Width Distortion (tPWD) as function of differential input voltage.
VRSET = VCCA - 1.5 V. (1) VCC = 5.5 V. (2) VCC = 3.0 V.
Fig.21 VRSET as function of junction temperature.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
MGR942
handbook, full pagewidth
200 mV/div
Fig.22 Differential output waveform with 4 mV differential input voltage.
MGR943
handbook, full pagewidth
200 mV/div
Fig.23 Differential output waveform with 2 V differential input voltage.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
APPLICATION INFORMATION
TZA3034
handbook, full pagewidth
VCC
100 nF VCCA 6 (11, 12) 1.5 nF DIN 4 (7)
180 k RSET 16 (30) CF 7 (13) Vref 15 (29) VCCD 14 (27, 28) (24) 13
100 nF
DOUT data out
data in 1.5 nF DINQ 5 (8) (3, 4, 6, 9) (1, 14) 3 1 AGND SUB
TZA3034
(23) 12 (16) 8 JAM (17) 9 STQ (18) (19, 20, 22, 25) 10 11 ST DGND DOUTQ
level detect status 1 k 50 50
MGR284
VCC - 2 V
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.24 Application diagram.
2002 Jul 19
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ewidth
2002 Jul 19
VCC
(1)
Philips Semiconductors
SDH/SONET STM1/OC3 postamplifier
680 nF
(1)
(1)
22 nF VCC 8 DREF OUTQ 31 pF 6 OUT 1.5 nF DIN
100 nF VCCA 6 (11, 12) 7 4 (7)
135 k RSET 16 (30) CF 7 (13) Vref 15 (29) VCCD 14 (27, 28) (24) 13
100 nF
1
DOUT data out
10 nF IPhoto 3
TZA3033T
100 1.5 nF
TZA3034
DINQ 5 (8) (3, 4, 6, 9) (1, 14) 3 1 AGND SUB (16) 8 JAM (17) 9 STQ (23) 12 (18) (19, 20, 22, 25) 10 11 ST DGND DOUTQ
2 GND
4 GND
5 GND
noise filter: 1-pole, 100 MHz
18
64.4 nH 29.2 pF 4.5 pF 1 k 50 50
level detect status
64.4 nH
MGR285
VCC - 2 V
optional noise filter: 3-pole, 120 MHz Bessel
Product specification
TZA3034
(1) Ferrite bead e.g. Murata BLM10A700S. The numbers in brackets refer to the pad numbers of the bare die version.
Fig.25 STM1/OC3 receiver using the TZA3033T and TZA3034.
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
BONDING PADS COORDINATES(1) SYMBOL SUB TEST AGND AGND n.c. AGND DIN DINQ AGND TEST VCCA VCCA CF SUB TEST JAM STQ ST DGND DGND TEST PAD X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -235.7 -392.8 -532.8 -647.8 -647.8 -647.8 -647.8 -647.8 -647.8 -647.8 -647.8 -532.8 -392.8 -235.7 -78.6 +61.4 +218.5 +375.6 +532.7 +647.8 +647.8 Y +647.8 +647.8 +647.8 +507.1 +350.0 +210.0 +70.0 -70.0 -210.0 -350.0 -507.1 -647.8 -647.8 -647.8 -647.8 -647.8 -647.8 -647.8 -647.8 -507.1 -350.0 DGND DOUTQ DOUT DGND TEST VCCD VCCD Vref RSET n.c. n.c. Note 22 23 24 25 26 27 28 29 30 31 32 SYMBOL PAD X +647.8 +647.8 +647.8 +647.8 +647.8 +647.8 +532.7 +392.7 +235.6 +78.5 -78.6
TZA3034
COORDINATES(1) Y -210.0 -70.0 +70.0 +210.0 +350.0 +507.1 +647.8 +647.8 +647.8 +647.8 +647.8
1. The x and y coordinates represent the position of the centre of the pad with respect to the centre of the die (see Fig.26).
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
AGND
SUB
3 AGND n.c. AGND 1.55(1) mm DIN DINQ AGND TEST VCCA 4 5 6 7 8 9 10 11 12 VCCA
2
1
32
31
30
29
Vref
handbook, full pagewidth
28 27 26 25 VCCD TEST DGND DOUT DOUTQ DGND TEST DGND
VCCD 24 23 22 21 20 19 DGND
MGR283
x 0 0 y
TZA3034U
13 CF
14 SUB
15 TEST
16 JAM
17 STQ
RSET
TEST
n.c.
n.c.
18 ST
1.55(1) mm
(1) Typical value.
Fig.26 Bonding pad locations of TZA3034U.
Table 1
Physical characteristics of bare die VALUE 2.1 m PSG (PhosphoSilicate Glass) on top of 0.65 m oxynitride minimum dimension of exposed metallization is 90 x 90 m (pad size = 100 x 100 m) 1.22 m W/AlCu/TiW 380 m nominal 1.55 x 1.55 mm (2.4 mm2) silicon; electrically connected to GND potential through substrate contacts <440 C; recommended die attache is glue <15 s
PARAMETER Glass passivation Bonding pad dimension Metallization Thickness Size Backing Attache temperature Attache time
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm
TZA3034
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
TZA3034
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
TZA3034
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
TZA3034
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products 2002 Jul 19 25 for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
NOTES
TZA3034
2002 Jul 19
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
NOTES
TZA3034
2002 Jul 19
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/04/pp28
Date of release: 2002
Jul 19
Document order number:
9397 750 09951

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